/* SPDX-License-Identifier: Apache-2.0 */
/*
 * Copyright (c) 2023 ASPEED Technology Inc.
 */

/* control registers */
#ifndef _LPTI_CTRL_H_
#define _LPTI_CTRL_H_

#include <linux/bitops.h>

/* control registers */
#define LTPI_LINK_ST				0x000
#define   REG_LTPI_LINK_ST_LOCAL		GENMASK(19, 16)
#define   REG_LTPI_LINK_ST_REMOTE		GENMASK(15, 12)
#define   REG_LTPI_LINK_SPEED			GENMASK(11, 8)
#define   REG_LTPI_LINK_DDR_MODE		BIT(7)
#define   REG_LTPI_LINK_ST_RESERVED		BIT(6)
#define   REG_LTPI_CON_ACC_TO_ERR		BIT(5)
#define   REG_LTPI_LINK_SP_TO_ERR		BIT(4)
#define   REG_LTPI_UNKNOWN_COMMA_ERR		BIT(3)
#define   REG_LTPI_FRM_CRC_ERR			BIT(2)
#define   REG_LTPI_LINK_LOST_ERR		BIT(1)
#define   REG_LTPI_LINK_ALIGN			BIT(0)

#define LTPI_CAP_LOCAL				0x004
#define   REG_LTPI_SP_CAP_LOCAL			GENMASK(23, 8)
#define   REG_LTPI_MAJOR_VER_LOCAL		GENMASK(7, 4)
#define   REG_LTPI_MIN_VER_LOCAL		GENMASK(3, 0)
#define LTPI_CAP_REMOTE				0x008
#define   REG_LTPI_SP_CAP_REMOTE		GENMASK(23, 8)
#define   REG_LTPI_MAJOR_VER_REMOTE		GENMASK(7, 4)
#define   REG_LTPI_MIN_VER_REMOTE		GENMASK(3, 0)
#define LTPI_PF_ID_LOCAL			0x00C
#define LTPI_PF_ID_REMOTE			0x010
#define LTPI_AD_CAP_LOW_LOCAL			0x014
#define LTPI_AD_CAP_HIGH_LOCAL			0x018
#define LTPI_AD_CAP_LOW_REMOTE			0x01C
#define LTPI_AD_CAP_HIGH_REMOTE			0x020
#define LTPI_DEFAULT_CON_LOW			0x024
#define LTPI_DEFAULT_CON_HIGH			0x028
#define LTPI_LINK_ALIGN_ERR_CNT			0x02C
#define LTPI_LINK_LOST_ERR_CNT			0x030
#define LTPI_CRC_ERR_CNT			0x034
#define LTPI_UNKNOWN_COMMA_ERR_CNT		0x038
#define LTPI_LINK_SP_TO_ERR_CNT			0x03C
#define LTPI_CON_ACC_TO_ERR_CNT			0x040
#define LTPI_LINK_TRAIN_RX_FRM_CNT_LOW		0x044
#define   REG_LTPI_CON_ACC_FRM_RX_CNT		GENMASK(31, 24)
#define   REG_LTPI_LINK_SP_FRM_RX_CNT		GENMASK(23, 16)
#define   REG_LTPI_LINK_DET_FRM_RX_CNT		GENMASK(15, 0)
#define LTPI_LINK_TRAIN_RX_FRM_CNT_HIGH		0x048
#define LTPI_LINK_TRAIN_TX_FRM_CNT_LOW		0x04C
#define   REG_LTPI_CON_ACC_FRM_TX_CNT		GENMASK(31, 24)
#define   REG_LTPI_LINK_SP_FRM_TX_CNT		GENMASK(23, 16)
#define   REG_LTPI_LINK_DET_FRM_TX_CNT		GENMASK(15, 0)
#define LTPI_LINK_TRAIN_TX_FRM_CNT_HIGH		0x050
#define LTPI_OP_RX_FRM_CNT			0x054
#define LTPI_OP_TX_FRM_CNT			0x058
#define LTPI_LINK_LOST_CNT			0x05c
#define   REG_LTPI_AD_ALIGN_TO_CNT		GENMASK(27, 24)
#define   REG_LTPI_LINK_LOST_OP_CNT		GENMASK(23, 16)
#define   REG_LTPI_LINK_LOST_CON_OR_ACC_CNT	GENMASK(15, 8)
#define   REG_LTPI_LINK_LOST_AD_CNT		GENMASK(7, 0)
#define LTPI_LINK_CONTROL			0x080
#define   REG_LTPI_TRIG_CON_ST			BIT(11)
#define   REG_LTPI_AUTO_CON_ST			BIT(10)
#define   REG_LTPI_DATA_CH_RST			BIT(9)
#define   REG_LTPI_I2C_RST			GENMASK(8, 2)
#define   REG_LTPI_LINK_RETRAIN_REQ		BIT(1)
#define   REG_LTPI_LINK_SW_RST			BIT(0)

#define LTPI_INTR				0x100
#define   REG_LTPI_LINK_HALT			BIT(24)
#define   REG_LTPI_DATA_CH_DROP_FRAME		BIT(23)
#define   REG_LTPI_DATA_CH_INVALID_ACCESS	BIT(22)
#define   REG_LTPI_I2C5_TO_ERR			BIT(21)
#define   REG_LTPI_I2C4_TO_ERR			BIT(20)
#define   REG_LTPI_I2C3_TO_ERR			BIT(19)
#define   REG_LTPI_I2C2_TO_ERR			BIT(18)
#define   REG_LTPI_I2C1_TO_ERR			BIT(17)
#define   REG_LTPI_I2C0_TO_ERR			BIT(16)
#define   REG_LTPI_AD_ALIGN_TO			BIT(12)
#define   REG_LTPI_HW_RETRY_LINK_DET_STUCK_TO_ERR BIT(11)
#define   REG_LTPI_HW_RETRY_TO_ERR		BIT(10)
#define   REG_LTPI_OP_LINK_LOST_ERR		BIT(4)
#define   REG_LTPI_CON_OR_ACC_LINK_LOST_ERR	BIT(3)
#define   REG_LTPI_AD_LINK_LOST_ERR		BIT(2)
#define   REG_LTPI_CON_READY			BIT(1)
#define   REG_LTPI_AD_READY			BIT(0)
#define LTPI_INTR_EN				0x104
#define   REG_LTPI_LINK_HALT_INTR_EN		BIT(24)
#define   REG_LTPI_DATA_CH_DROP_FRAME_EN	BIT(23)
#define   REG_LTPI_DATA_CH_INVALID_ACCESS_EN	BIT(22)
#define   REG_LTPI_I2C5_TO_ERR_EN		BIT(21)
#define   REG_LTPI_I2C4_TO_ERR_EN		BIT(20)
#define   REG_LTPI_I2C3_TO_ERR_EN		BIT(19)
#define   REG_LTPI_I2C2_TO_ERR_EN		BIT(18)
#define   REG_LTPI_I2C1_TO_ERR_EN		BIT(17)
#define   REG_LTPI_I2C0_TO_ERR_EN		BIT(16)
#define   REG_LTPI_AD_ALIGN_TO_EN		BIT(12)
#define   REG_LTPI_HW_RETRY_LINK_DET_STUCK_TO_ERR_EN BIT(11)
#define   REG_LTPI_HW_RETRY_TO_ERR_EN		BIT(10)
#define   REG_LTPI_CON_ACC_TO_ERR_EN		BIT(9)
#define   REG_LTPI_LINK_SP_TO_ERR_EN		BIT(8)
#define   REG_LTPI_UNKNOWN_COMMA_ERR_EN		BIT(7)
#define   REG_LTPI_FRM_CRC_ERR_EN		BIT(6)
#define   REG_LTPI_LINK_LOST_ERR_EN		BIT(5)
#define   REG_LTPI_OP_LINK_LOST_ERR_EN		BIT(4)
#define   REG_LTPI_CON_OR_ACC_LINK_LOST_ERR_EN	BIT(3)
#define   REG_LTPI_AD_LINK_LOST_ERR_EN		BIT(2)
#define   REG_LTPI_CON_READY_EN			BIT(1)
#define   REG_LTPI_AD_READY_EN			BIT(0)
#define LTPI_LINK_MNG_ST			0x108
#define   REG_LTPI_LINK_PARTNER_FLAG		BIT(24)
#define     REG_LTPI_LINK_PARTNER_FPGA		0b0
#define     REG_LTPI_LINK_PARTNER_1700		0b1
#define   REG_LTPI_SP_INTERSETION		GENMASK(23, 8)
#define   REG_LTPI_LINK_MNG_ST			GENMASK(3, 0)
#define     LTPI_LINK_MNG_ST_DETECT_ALIGN	0
#define     LTPI_LINK_MNG_ST_DETECT		1
#define     LTPI_LINK_MNG_ST_SPEED		2
#define     LTPI_LINK_MNG_ST_WAIT_PLL_SET	3
#define     LTPI_LINK_MNG_ST_ADV_ALIGN		4
#define     LTPI_LINK_MNG_ST_ADV		5
#define     LTPI_LINK_MNG_ST_CONFIG_ACC		6
#define     LTPI_LINK_MNG_ST_OP			7
#define LTPI_LINK_MANAGE_CTRL0			0x10C
#define   REG_LTPI_LINK_PARTNER_CHKNUM		GENMASK(19, 16)
#define   REG_LTPI_CON_FRM_NOCHK		BIT(8)
#define   REG_LTPI_TX_LINK_SP_FRM_NUM		GENMASK(7, 4)
#define   REG_LTPI_RX_LINK_SP_FRM_NUM		GENMASK(3, 0)
#define LTPI_LINK_MANAGE_CTRL1			0x110
#define LTPI_LINK_MANAGE_CTRL2			0x114
#define LTPI_CON_CAP_LOW			0x118
#define LTPI_CON_CAP_HIGH			0x11C
#define LTPI_MAC_CTRL				0x120
#define LTPI_AHB_CTRL0				0x124
#define   REG_LTPI_AHB_ADDR_MAP1		GENMASK(25, 16)
#define   REG_LTPI_AHB_ADDR_MAP0		GENMASK(9, 0)
#define LTPI_AHB_CTRL1				0x128
#define   REG_LTPI_AHB_ADDR_MAP3		GENMASK(25, 16)
#define   REG_LTPI_AHB_ADDR_MAP2		GENMASK(9, 0)
#define LTPI_CRC_OPTION				0x12c
#define   REG_LTPI_SW_CRC_OUT_ML_FIRST		BIT(2)
#define   REG_LTPI_SW_CRC_IN_LSB_FIRST		BIT(1)
#define   REG_LTPI_CRC_SW_FORCE			BIT(0)
#define LTPI_I2C				0x130
#define   REG_LTPI_I2C_SLV_MST_SWITCH_SW_EN	BIT(8)
#define   REG_LTPI_I2C_SLV_EN			GENMASK(5, 0)

#define LTPI_OEM_BUS_SETTING			0x188
#define   REG_LTPI_OEM_RX_START_TRIG		BIT(1)
#define   REG_LTPI_OEM_TX_START_TRIG		BIT(0)

#define LTPI_OEM_DBG0				0x190
#define   REG_LTPI_OEM_RX_INIT_DONE		BIT(9)
#define   REG_LTPI_OEM_TX_INIT_DONE		BIT(8)

#define LTPI_DATA_CH_CFG0                       0x1D8
#define   REG_LTPI_DATA_CH_TAG_CHK_EN		BIT(2)
#define   REG_LTPI_DATA_CH_ADDR_CHK_EN		BIT(1)
#define   REG_LTPI_DATA_CH_WAIT_ACK_TO_EN	BIT(0)

#endif	/* _LPTI_CTRL_H_ */
